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NXP Semiconductors /MIMXRT1011 /GPT1 /IR

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Interpret as IR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OF1IE)OF1IE 0 (OF2IE)OF2IE 0 (OF3IE_0)OF3IE 0 (IF1IE)IF1IE 0 (IF2IE_0)IF2IE 0 (ROVIE_0)ROVIE

ROVIE=ROVIE_0, OF3IE=OF3IE_0, IF2IE=IF2IE_0

Description

GPT Interrupt Register

Fields

OF1IE

See OF3IE
OF2IE

See OF3IE
OF3IE

OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt

0 (OF3IE_0): Output Compare Channel n interrupt is disabled.

1 (OF3IE_1): Output Compare Channel n interrupt is enabled.
IF1IE

See IF2IE
IF2IE

IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable

0 (IF2IE_0): IF2IE Input Capture n Interrupt Enable is disabled.

1 (IF2IE_1): IF2IE Input Capture n Interrupt Enable is enabled.
ROVIE

Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt.

0 (ROVIE_0): Rollover interrupt is disabled.

1 (ROVIE_1): Rollover interrupt enabled.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data